Details

Digital VLSI Design with Verilog

A Textbook from Silicon Valley Polytechnic Institute
2nd ed. 2014

von: John Michael Williams
117,69 €
Verlag:	Springer
Format:	PDF
Veröffentl.:	17.06.2014
ISBN/EAN:	9783319047898
Sprache:	englisch

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Beschreibungen

Titelbeschreibung

This book is structured as a step-by-step course of study along the lines of a VLSI integrated circuit design project. The entire Verilog language is presented, from the basics to everything necessary for synthesis of an entire 70,000 transistor, full-duplex serializer-deserializer, including synthesizable PLLs. The author includes everything an engineer needs for in-depth understanding of the Verilog language: Syntax, synthesis semantics, simulation and test. Complete solutions for the 27 labs are provided in the downloadable files that accompany the book. For readers with access to appropriate electronic design tools, all solutions can be developed, simulated, and synthesized as described in the book. A partial list of design topics includes design partitioning, hierarchy decomposition, safe coding styles, back annotation, wrapper modules, concurrency, race conditions, assertion-based verification, clock synchronization, and design for test. A concluding presentation of special topics includes System Verilog and Verilog-AMS.

Inhaltsverzeichnis

Introductory Material.- Week 1 Class 1.- Week 1 Class 2.- Week 2 Class 1.- Week 2 Class 2.- Week 3 Class 1.- Week 3 Class 2.- Week 4 Class 1.- Week 4 Class 2.- Week 5 Class 1.- Week 5 Class 2.- Week 6 Class 1.- Week 6 Class 2.- Week 7 Class 1.- Week 7 Class 2.- Week 8 Class 1.- Week 8 Class 2.- Week 9 Class 1.- Week 9 Class 2.- Week 10 Class 1.- Week 10 Class 2.- Week 11 Class 1.- Week 11 Class 2.- Week 12 Class 1.- Week 12 Class 2.

Autorenportrait

After spending some years at sea in the U. S. Navy, John Michael Williams returned to school for degrees at Columbia University, the University of Chicago and Southern Illinois University, eventually studying human vision in postdoctoral study at the University of Michigan. He moved to California in 1982 and spent significant work time as an applications engineer at Daisy Systems and then at Compass Design Automation. After attending various physics-related classes at Stanford, he began teaching at Silicon Valley Technical Institute, where he wrote the first edition of "Digital VLSI Design with Verilog" and many other course workbooks which now are posted at Scribd. He moved to Oregon a few years ago, where he remains mostly retired.

Back cover copy

This book is structured as a step-by-step course of study along the lines of a VLSI integrated circuit design project. The entire Verilog language is presented, from the basics to everything necessary for synthesis of an entire 70,000 transistor, full-duplex serializer-deserializer, including synthesizable PLLs. The author includes everything an engineer needs for in-depth understanding of the Verilog language: Syntax, synthesis semantics, simulation, and test. Complete solutions for the 27 labs are provided in the downloadable files that accompany the book. For readers with access to appropriate electronic design tools, all solutions can be developed, simulated, and synthesized as described in the book. A partial list of design topics includes design partitioning, hierarchy decomposition, safe coding styles, back annotation, wrapper modules, concurrency, race conditions, assertion-based verification, clock synchronization, and design for test. A concluding presentation of special topics includes SystemVerilog and Verilog-AMS. <ul><li>Covers the entire Verilog language – using most of it in practice;</li><li>Provides 27 lab exercises, with complete and tested answers;</li><li>Explains and emphasizes synthesizability, wherever it pertains to language features;</li><li>Develops as a major project a synthesizable 70,000-gate SerDes;</li><li>Presents synthesis-relevant usage of SystemVerilog, and the basic functionality of Verilog-AMS.</li></ul>>

Sonderbeitrag

Covers the entire Verilog language – using most of it in practice Provides 27 lab exercises, with complete and tested answers Explains and emphasizes synthesizability, wherever it pertains to language features Develops as a major project a synthesizable 70,000-gate Ser Des Presents synthesis-relevant usage of System Verilog and the basic functionality of Verilog-AMS Includes supplementary material: sn.pub/extras